1. Field of the Invention
The present invention relates to an electrically writable, non-volatile memory.
2. Description of the Background Art
A conventional non-volatile memory is made up of a memory cell array, a row decoder, a column decoder, a cell drain voltage (CDV) generator and a VPP circuit, as disclosed for example by the Japanese Patent Laid-Open Publication No. 68683/1994 and U.S. Pat. No. 6,088,265 to Ohta. The memory cell array thus disclosed is comprised of a plurality of memory cells interconnected to a plural number of word lines and a plural number of bit lines. The row decoder is adapted to define a row address to control the appropriate gate electrodes, or word lines, of the memory cell array, and the column decoder is to define a column address to control the appropriate source electrodes, or bit lines, thereof. The CDV generator supplies the cell drain voltage (CDV) to the drain electrodes of the memory cells, and the VPP circuit supplies a high voltage VPP to the row decoder.
During the write operation, the row decoder is responsive to an address signal Ain to apply the voltage VPP to an appropriate word line. The column decoder selects an appropriate bit position. For readout, the CDV generator supplies a ground (GND) level voltage (voltage 0[V]) to the drain electrode of a memory cell, while, for writing, the CDV generator supplies a voltage level VCC to the drain electrode of the memory cell.
As such a non-volatile memory, there are disclosed by for example U.S. Pat. No. 6,233,168 to Kokubun et al., the configuration of a non-volatile memory having four drain lines and a readout method therefor.
However, in the conventional system for writing in such memory cells, one of two drain electrodes is selected to apply an electrical voltage CDV thereto with the non-selected drain electrode being in its open state. Thus, a voltage equal to (CDV−threshold voltage Vt)/2 is generated even at the drain electrode of a memory cell which is not the target for writing. Consequently, there is fear that erroneous writing may occur in a memory cell which is not intended to be selected.
For example, with the voltage VCC of 4.4 V and the threshold voltage Vt of approximately 0.8 V, there is caused a difference in potential of approximately 1.8 V on a path between the source and drain electrodes of a memory cell by the voltage equal to (CDV−threshold voltage Vt)/2. In such a case, there is fear that erroneous writing may take place because the current flows through the memory cell.
On the other hand, the above patent publications teach the method of readout but fail to disclose a method for writing which will prevent erroneous writing in memory cells.